1. Technical Field
The present invention relates generally to timing analysis of an array, and in particular, to a computer implemented method for timing analysis of a cross section of an array circuit design.
2. Description of Related Art
Semiconductor memory designers test their circuit designs to check for a variety of issues including functionality, robustness and timing prior to having those designs implemented in silicon. For memory arrays, these circuit designs may be a schematic design in combination with a layout design. For testing, a netlist is extracted from the circuit design. A netlist generally conveys connectivity information and may include instances, nets and their attributes. An instance is a description of a part or device such as a transistor, resistor, capacitor or integrated circuit and may include a description of the device, the connections that can be made (“pins”) to the device, and the basic properties of the device. Nets are the wires that connect instances in the designed circuit. There may be attributes associated with nets. A netlist is a compilation of the instances, nets and their attributes which describe the devices and connections between those devices within a circuit design.
Various types of testing may be performed on a netlist of the circuit design. One type of test is design verification to determine whether the circuit is functional and robust. Various software tools such as SPICE modeling may be used for design verification. Another type of test is static timing analysis for determining circuit performance and identifying timing constraints while accounting for variations in the technology process used to manufacture the circuit (process corners). Static timing analysis is a method of computing the expected timing of a circuit without requiring simulation. Various types of testing software may be used for performing timing analysis of a circuit design.
Testing a full extracted netlist of the whole circuit design such as static timing analysis could be prohibitively expensive and time consuming. As a result, designers may create a cross section netlist of their circuit design for testing purposes. Designers will try to create these cross section netlists so that the electrical and timing properties of the cross section netlist closely match those of a full extracted circuit design netlist. However, creating a cross section netlist is often time consuming and may not match the characteristics of the underlying circuit design.